1. Field of the Invention
The present invention relates to a semiconductor verification apparatus, method and program.
2. Description of the Related Art
With the development of semiconductor technology, an integration degree of a semiconductor device (logical Large Scale Integrated circuit (LSI)) is so improving every year that a large scale system can be integrated in one chip. Since the production cost of a semiconductor device is, however, becoming higher and a large amount of time is needed for producing the semiconductor device, it is important to execute sufficient verification before the production starts.
A verification of a semiconductor device is executed at various phases of the design. A design process takes many steps from a notional level at an initial design to a detailed production level at a final step, and handles logical information appropriate for each level. For example, logical information fit for the notional level to establish input-output relation or the like is handled at the initial design step, logical information fit for the function level to determine functions of each logic section is handled at the functional design step, and logical information fit for the structure level to determine logical structure is handled at the final detailed design step. The logical information fit for the aforementioned various design steps can be expressed with each type of hardware description languages (such as SystemC, SystemVerilog, Verilog-HDL, and VHDL) generally used.
As methods of verifying system logics using a semiconductor device or a plurality of semiconductor devices, there are a method with software simulators, a method with hardware emulators, and a method with actual semiconductor devices utilized. Software simulators can be used at various design steps because they run logical information described in hardware description language as a computer program. Furthermore, the software simulators have an advantage such that all of variable values in the hardware description language can be easily observed because they run behavior of circuits as a computer program.
Meanwhile, the actual semiconductor devices and the hardware emulators are hardware, and thus, they can run logical operation faster than the software simulators. The hardware emulators are devices which generally comprise rewritable hardware such as Field Programmable Gate Array (FPGA) and Field Programmable Interconnect Device (FPID). However, a problem with general semiconductor devices and hardware emulators is that they have difficulty in observing all signals due to cost constraints and hardware restrictions and so on, and difficulty in debugging circuits.
As a means for solving the problem herewith, disclosed is a technique for loading logical values of arbitrary memory elements implemented in FPGA without special support of hardware by controlling such a read-back function present in FPGA through JTAG (IEEE1149.1) as described in Patent Documents 1 and 2. Using the technique herein can help to drastically reduce the problem of an observability relating to the hardware emulators as described above.    Patent Document 1: Japanese Patent Application Laid-Open No. 2005-174349, paragraph 0055    Patent Document 2: Japanese Patent Application No. 2006-553063, paragraph 0085    Non-Patent Document 1: Virtex-4, Configuration Guide v1.10 published by Xilinx, Inc.